发明名称 In-situ process layer using silicon-rich-oxide for etch selectivity in high AR gapfill
摘要 In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps with significantly reduced incidence of voids or weak spots is provided. This deposition part of the process may involve the use of any suitable high density plasma chemical vapor deposition (HDP CVD) chemistry. Prior to etch back, the feature gap is plugged with an etch selectivity layer. The etch back part of the process involves multiple steps including a sputter etch to reduce the top hat formations followed by a reactive plasma etch to open the gap. This method improves gapfill, reduces the use of high cost fluorine-based etching and produces interim gaps with better sidewall profiles and aspect ratios.
申请公布号 US7951683(B1) 申请公布日期 2011.05.31
申请号 US20070697611 申请日期 2007.04.06
申请人 NOVELLUS SYSTEMS, INC 发明人 SHANKER SUNIL
分类号 H01L21/76 主分类号 H01L21/76
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