发明名称 Digital noise filter
摘要 A digital noise filter circuit includes a gating clock generating circuit and a noise filter circuit. The gating clock generating circuit compares logic levels of an input signal and an output signal of the noise filter circuit. The gating clock generating circuit supplies a gating clock as an operating clock to the noise filter circuit when the logic levels of both signals do not coincide, and halts supply of the gating clock when the logic levels of both signals do coincide. The noise filter circuit removes noise from the input signal and outputting the resultant signal as the output signal.
申请公布号 US7952391(B2) 申请公布日期 2011.05.31
申请号 US20100785652 申请日期 2010.05.24
申请人 RENESAS ELECTRONICS CORPORATION 发明人 YAMAGUCHI RYOICHI
分类号 H03K19/00 主分类号 H03K19/00
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