发明名称 Semiconductor integrated circuit including power domains
摘要 A scan chain configuration and a control method for the same are provided, which are optimized for the leakage current reduction technique by a vector input in SoC in which many functional blocks are mounted. The semiconductor integrated circuit includes: plural power domains (Area1-AreaN) which have plural functional blocks; power switches (PSW1-PSWN) which can supply a power source for operation to the power domains; a scan chain provided for every power domain, and a memory unit (VEC) which supplies, to a scan chain, a vector to enable shifting to a low-leakage state. By re-coupling the scan chain only to a non-operating functional block, it is possible to perform shifting to a low-leakage state for a short time.
申请公布号 US7954023(B2) 申请公布日期 2011.05.31
申请号 US20080342015 申请日期 2008.12.22
申请人 RENESAS ELECTRONICS CORPORATION 发明人 OTSUGA KAZUO;OSADA KENICHI;KANNO YUSUKE
分类号 G01R31/28 主分类号 G01R31/28
代理机构 代理人
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