| 摘要 |
<p>A serializing and deserializing method is disclosed The method involves setting a frame format for encoding serial data with a channel number N as a variable (101), a local receiving side locating a frame head for the received serial data according to the set frame format (102), and converting the serial data into N-bit parallel data (103), parsing parallel data to obtain link status according to the set frame format, and outputting the N-bit parallel data, a local sending side encoding local parallel data according to the set frame format, and outputting the parallel data in corresponding frame format according to the link status obtained through parsing by the local receiving side, converting the parallel data into serial data, and outputting the serial data with a frequency-multiplied high-speed clock There is also disclosed a serializing and deserializing apparatus With the method and apparatus applied, conversion to each other between a serial signal and parallel signals of different channel numbers can be implemented in a Field Programmable Gate Array (FPGA) module, thereby reducing user consumption costs</p> |
