发明名称 |
CUSTOMIZED PATTERNING MODULATION AND OPTIMIZATION |
摘要 |
The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical parameter of the circuit and an optical parameter of IC design layout; and thereafter fabricating a mask according to the IC design layout.
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申请公布号 |
US2011124193(A1) |
申请公布日期 |
2011.05.26 |
申请号 |
US20090625749 |
申请日期 |
2009.11.25 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
CHENG YING-CHOU;LIU RU-GUN;FENG JOSH J.H.;OU TSONG-HUA;LO LUKE;LAI CHIH-MING;HUANG WEN-CHUN |
分类号 |
H01L21/033;G06F17/50 |
主分类号 |
H01L21/033 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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