| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a word line decoding and a selection architecture. <P>SOLUTION: A flash memory includes: first sectors 202, 204 and second sectors 206, 208 of memory cells; first local driver circuits 210, 212 and second local driver circuits 214, 216; a first decoding circuit 218, second decoding circuits 222, 224 and third decoding circuits 226, 228; and a driver circuit 220. The first decoding circuit activates the plurality of first local driver circuits, and the second decoding circuit activates the plurality of second local driver circuits 214, 216. The second decoding circuits are coupled to the first local driver circuits. The third decoding circuits are coupled to the second local driver circuits and supply a second boosted voltage to a second selected word line. The driving circuit supplies the boosted voltages to the first, second and third decoding circuits and the first and second local driver circuits. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
