| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce a frequency of occurrence of erroneous readout while suppressing the increase of a circuit scale even when a failure of a bit cell after writing occurs at random. <P>SOLUTION: The same data is written into a plurality of bit cells BC having the same bit lines BL<0> to BL<m-1> and different word lines WL<0> to WL<n-1>, and an address buffer 1 instructs to a row decoder 2 at the readout so that the data is simultaneously read out from the plurality of bit cells BC having the same bit lines BL<0> to BL<m-1> and different word lines WL<0> to WL<n-1>. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
