<p>Described herein are novel, cost effective and scalable methods for integrating a CMOS level with a memory cell level forming a field induced MRAM device. The memory portion of the device includes N parallel word lines overlaid by M parallel bit lines orthogonal to the word lines and individual patterned memory cells formed on previously patterned electrodes at the NxM intersections of the two sets of lines. The memory portion is integrated with a CMOS level and the connection between levels is facilitated by the formation of interconnecting vias between the NxM electrodes and corresponding pads in the CMOS level and by word line connection pads in the memory device level and corresponding metal pads in the CMOS level.</p>
