发明名称 |
POWER-MODE-AWARE CLOCK TREE AND SYNTHESIS METHOD THEREOF |
摘要 |
A power-mode-aware (PMA) clock tree and a synthesis method thereof are provided. The clock tree includes a sub clock tree and a PMA buffer. The sub clock tree transmits a delayed clock signal to a function module, wherein a power mode of the function module is determined according to a power information. The PMA buffer is coupled to the sub clock tree. The PMA buffer determines the delay time of a system clock signal according to the power information delays the system clock signal, and outputs the delayed system clock signal to the sub clock tree as the delayed clock signal.
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申请公布号 |
US2011121875(A1) |
申请公布日期 |
2011.05.26 |
申请号 |
US20100750721 |
申请日期 |
2010.03.31 |
申请人 |
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE;NATIONAL TSING HUA UNIVERSITY |
发明人 |
LUNG CHIAO-LING;CHANG SHIH-CHIEH |
分类号 |
H03L7/00;G06F17/50 |
主分类号 |
H03L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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