发明名称 Circuit for undisturbed clock signal switching
摘要 <p>The circuit has a NOX logic gate (104) for outputting the synchronization signal (105) according to NOX logic function between clock signals (101, 102). A D flip-flop type logic circuit (106) receives the signal (105) and a signal (108) from a frequency detector (107), and produces a control signal (109) at the destination of a clock switch (103) piloting the switching between the signals (101, 102), such that a clock signal (110) is equal to the signals (101, 102) when the frequency of the signal (101) is equal to low and high clock frequencies (F1, F2) of the signal (101), respectively.</p>
申请公布号 EP2326004(A1) 申请公布日期 2011.05.25
申请号 EP20100190702 申请日期 2010.11.10
申请人 THALES 发明人 SAINT ELLIER, PIERRE;GEAIRON, SEBASTIEN;COMMUN, PASCAL
分类号 H03K5/135;H03K5/26 主分类号 H03K5/135
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