发明名称
摘要 <p>A switch operating in a multistage switch network is provided. The switch includes a plurality of ports, a first processor for processing a source address and a destination address of a packet received by the plurality of ports, and a second processor for including a memory storing data of the packet, and for outputting, under the control of the first processor, the data of the packet stored on the memory, wherein the first processor calculates a hash value of the source addresses of the packet in accordance with a specific hash function, identifies a output port connected to a switch that corresponds to the hash value and is to learn the source address, and causes the second processor to output the data of the packet to the output port.</p>
申请公布号 JP4688946(B2) 申请公布日期 2011.05.25
申请号 JP20090141874 申请日期 2009.06.15
申请人 发明人
分类号 H04L12/44 主分类号 H04L12/44
代理机构 代理人
主权项
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