发明名称 Package substrate structure and chip package structure and manufacturing process thereof
摘要 A chip package structure includes a substrate, chips and an elastic element. The substrate has a first surface, a second surface, a first patterned metal layer on the first surface and a second patterned metal layer on the second surface, wherein the substrate is suitable for being clipped between an upper mold chase and a lower mold chase of a package mold. The chips are disposed on the first surface, wherein the chips are suitable for being contained in containing spaces defined by the upper mold chase and the substrate. The elastic element is disposed on the second surface and surrounds the second patterned metal layer, wherein the elastic element is suitable for contacting the lower mold chase and is located between the lower mold chase and the substrate. In addition, a manufacturing process of the chip package and a package substrate structure are also provided.
申请公布号 EP2211377(A3) 申请公布日期 2011.05.25
申请号 EP20100151430 申请日期 2010.01.22
申请人 EVERLIGHT ELECTRONICS CO., LTD. 发明人 TSOU, WEN-CHIEH
分类号 H01L21/56;H01L23/31 主分类号 H01L21/56
代理机构 代理人
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