| 摘要 |
An error detecting/correcting code generating circuit includes a first exclusive OR operation circuit that generates log 2 (n+1) bits of one portion of a redundant portion of error detecting/correcting-code-attached data by rounding up the numbers to the right of the decimal point of log 2 (n+1) in response to the input of m bytes of an information portion included in error-detection-bit-attached data. The error-detection-bit-attached data includes a redundant portion of m bits of error detection bits allocated to the m bytes of the information portion, the byte having n bits. The circuit also includes a second exclusive OR operation circuit that generates m bits of another portion of the redundant portion of the error detecting/correcting-code-attached data in response to the input of the one portion and the error detection bits. |
