发明名称 DRAM device having a gate dielectric layer with multiple thicknesses
摘要 A transistor device employed in a support circuit of a DRAM includes a semiconductor substrate having thereon a gate trench, a recessed gate embedded in the gate trench, a source doping region disposed at one side of the recessed gate, a drain doping region disposed at the other side of the recessed gate, and a gate dielectric layer between the recessed gate and the semiconductor substrate. The gate dielectric layer has at least two thicknesses that render the high-voltage transistor device asymmetric. The thicker gate dielectric layer is between the recessed gate and the drain doping region, while the thinner gate dielectric layer is between the recessed gate and the source doping region.
申请公布号 US7948028(B2) 申请公布日期 2011.05.24
申请号 US20080049385 申请日期 2008.03.17
申请人 NANYA TECHNOLOGY CORP. 发明人 RENN SHING-HWA
分类号 H01L29/66 主分类号 H01L29/66
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