发明名称 |
Transparent level 2 cache controller |
摘要 |
A digital system that connects to a bus that employs physical addresses comprises a processing core. A level one (L1) cache communicates with the processing core. A level two (L2) cache communicates with the L1 cache. Both the L1 cache and the L2 cache are indexed by virtual addresses and tagged with virtual addresses. A bus unit communicates with the L2 cache and with the bus.
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申请公布号 |
US7949833(B1) |
申请公布日期 |
2011.05.24 |
申请号 |
US20100728583 |
申请日期 |
2010.03.22 |
申请人 |
MARVELL INTERNATIONAL LTD. |
发明人 |
CHEN HONG-YI;YUNG GEOFFREY K. |
分类号 |
G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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