发明名称 Hierarchy encoding apparatus and hierarchy encoding method
摘要 A hierarchy encoding apparatus capable of calculating appropriate delay amounts and also capable of suppressing increase in the bit rate. In this apparatus, a first layer encoding part (101) encodes the input signal of the n-th frame to produce a first layer encoded code. A first layer decoding part (102) generates a first layer decoded signal from the first layer encoded code and applies it to a delay amount calculating part (103) and a second layer encoding part (105). The delay amount calculating part (103) uses the first layer decoded signal and input signal to calculate the delay amount to be added to the input signal, and applies the calculated delay amount to a delay part (104). The delay part (104) delays the input signal by the delay amount applied from the delay amount calculating part (103) and then applied it to a second layer encoding part (105). The second layer encoding part (105) uses the first layer decoded signal and the input signal from the delay part (104) for encoding.
申请公布号 US7949518(B2) 申请公布日期 2011.05.24
申请号 US20060587495 申请日期 2006.10.26
申请人 PANASONIC CORPORATION 发明人 OSHIKIRI MASAHIRO
分类号 G06F15/00;G10L11/00;G10L11/06;G10L19/02;G10L19/14;H03M7/30 主分类号 G06F15/00
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