| 摘要 |
A clock synchronizer for generating a local clock signal synchronized to a received clock signal. The clock synchronizer incorporates a reference oscillator providing a reference signal, and a synthesizer circuit arranged to synthesize a local clock signal from the reference signal. The synthesizer circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchronizer also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and received clock signals. A control link is arranged to link the clock comparison circuit to the divider. This link receives the digital signal and provides a control signal to the divider to adjust the frequency division value N according to the digital signal, to alter the local clock frequency and reduce the asynchronism.
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