发明名称 ASIC VERIFICATION APPARATUS AND IMAGE FORMING APPARATUS
摘要 <P>PROBLEM TO BE SOLVED: To enable circuit verification for large scale SoC (System on a Chip) using a small scale FPGA (Field Programmable Gate Array). <P>SOLUTION: An ASIC verification apparatus includes: a writing means having two or more PROMs 106 storing module circuit information, a selector 109 for selecting a memory storing module circuit information serving as the subject of verification, an FPGA (Field Programmable Gate Array) 101 with a CPU 102, and a main memory 107, and adapted for writing the module circuit information stored in the memory 106 selected by the selector 109 to the FPGA 101; a verification means for conducting module operation verification based on the module circuit information written to the FPGA 101 by the writing means; and a storage means for storing data after verification by the verification means, the boot program of the CPU, and a test program for the next module circuit to be verified in the main memory 107. <P>COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011100351(A) 申请公布日期 2011.05.19
申请号 JP20090255316 申请日期 2009.11.06
申请人 RICOH CO LTD 发明人 HARADA YASUNARI
分类号 G06F11/22;G06F3/12 主分类号 G06F11/22
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