发明名称
摘要 Certain aspects of the present disclosure relate to a method for employing a special format for transmitting data blocks which allows parallel equalizations at a receiver. By applying parallel equalization operations, a clock at the receiver can operate at a fraction of the input signal's data rate, which is more practical in the case of very high data rates while power dissipation is also reduced.
申请公布号 JP2011515954(A) 申请公布日期 2011.05.19
申请号 JP20110500908 申请日期 2009.03.17
申请人 发明人
分类号 H04B7/005 主分类号 H04B7/005
代理机构 代理人
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