| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device to which a power device and a CMOS device can be mounted mixedly while enhancing the avalanche resistance and ESD resistance of the power device. SOLUTION: A P-type well 12 is formed at the upper part of a semiconductor substrate 11, an STI13 is provided selectively at the well 12, and an N<SP>+</SP>-type source layer 17 and a drain layer 18 are formed in an opening 14 of the STI13 to touch the side surface 13a of the STI 13 and to be separated from each other. A P<SP>+</SP>-type contact layer 19 is formed between the source layer 17 and the drain layer 18. The contact layer 19 is formed to touch the source layer 17 and to be separated from the STI13. Furthermore, a source electrode 21 is connected to the source layer 17 and the contact layer 19, a drain electrode 22 is connected to the drain layer 18, and a gate electrode 23 is formed on the STI13 along the side surface 13a. COPYRIGHT: (C)2011,JPO&INPIT
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