| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce access frequency to a tag memory and a data memory in a set-associative system cache device. <P>SOLUTION: A cache device includes: a data memory including a plurality of ways which store a part of the data of main memory; a tag memory including a plurality of ways each of which stores a tag included in the address of the data recorded in each of the ways of the data memory; a comparator circuit which determines whether the tag included in an access object address is matched with the tag recorded in the tag memory; a next address generation part which calculates a second address to be accessed the next by referring to the first address to be accessed this time; and a tag reading control circuit which performs read-ahead of the tag corresponding to the index of the second address from the tag memory, and which, when the tag included in the second address is matched with the read-ahead tag, prevents the following tag from being read from the tag memory. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
