| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a logic circuit design support method for achieving gated clock design for reducing power consumption in an actual operation. <P>SOLUTION: The logic circuit design support method includes: a first step S1 for extracting information D2 of a plurality of enable signals input to an optimization object logic circuit on the basis of circuit data D1 described in the circuit structure of the optimization object logic circuit; a second step S2 for executing the logic simulation of an actual operation mode to the optimization object logic circuit and the generation logic of the extracted enable signals, and for acquiring time series information D4 related with state transition between an active state and an inactive state in the operation of each enable signal; and third steps S3 to S5 for optimizing the number of insertion and the place of insertion of a clock gating circuit so that the total power consumption of the optimization object logic circuit and the clock gating circuit can be made smaller than the power consumption of the optimization object logic circuit before the clock gating circuit is inserted on the basis of the time series information D4. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
