METHOD, LOGICAL DEVICE AND SYSTEM FOR CALCULATING JITTER OF CIRCUIT, AND METHOD, LOGICAL DEVICE AND SYSTEM FOR SYNTHESIZING CLOCK TREE OF CIRCUIT

摘要

PROBLEM TO BE SOLVED: To cope with a problem related to a chip level design, and to calculate accurate path delay even when crosstalk coupling exists. SOLUTION: In a method for calculating jitter in a clock tree in one embodiment, the clock tree is divided into a plurality of stages, and the jitter in one or more of the stages is calculated according to a model of at least a part of a circuit associated to the clock tree. The model includes representation of each source of the jitter of the circuit. The method includes a step of statistically synthesizing the jitter in each stage of a path or a pair of paths inside the clock tree with each other to calculate the jitter associated to the path or the pair of paths inside the clock tree. In one embodiment, to efficiently calculate the jitter and to achieve clock skew zero, a model synthesizes a symmetrical clock tree of the circuit in which corresponding stages in all paths from a root of the clock tree to sinks of the clock tree exhibit properties approximately electrically equivalent to each other. COPYRIGHT: (C)2011,JPO&INPIT