发明名称 CONTROLLER FOR IMAGE PROCESSOR
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a technology for combining power saving and high speed of an image processor more appropriately. <P>SOLUTION: This controller for an image processor having a function of switching a plurality of operation modes includes a CPU predetermined in the ON/OFF frequency of a power source guaranteed in operation; a sub-CPU controlling switching from a power-saving mode to a normal mode; and other devices. In the power-saving mode, the CPU is set into a sleep state, and the sub-CPU is set into an ON-state in which the usual function can be carried out. The other devices are set into the sleep state or the power OFF state. When predetermined conditions based on the ON/OFF frequency of a power source of the CPU are established, the power source of the CPU is set into the OFF state. <P>COPYRIGHT: (C)2011,JPO&INPIT</p>
申请公布号 JP2011098561(A) 申请公布日期 2011.05.19
申请号 JP20100120090 申请日期 2010.05.26
申请人 SEIKO EPSON CORP 发明人 TAKAGI TOSHIMITSU
分类号 B41J29/38;G03G21/00;G06F1/32 主分类号 B41J29/38
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