| 摘要 |
PROBLEM TO BE SOLVED: To reduce an overall size by further decreasing a gate area not only by simplifying an entire configuration but also by accelerating an operating speed. SOLUTION: A pseudo-orthogonal code generator includes: a serial/parallel converter for converting serial transmission data into parallel data for the unit of nine bits; a four-bit counter for repeatedly counting from 0 to 15; and a combination circuit unit for sequentially generating a pseudo-orthogonal code of 16 bits using the parallel data of nine bits and a four-bit counter value. Signal processing in the combination circuit unit is represented by a predetermined expression (0≤I≤15) of cb0(I), cb1(I), cb2(I), cb3(I), C(I) wherein C(I) is 0≤I≤15 as a pseudo-orthogonal code for the parallel data of nine bits, b0-b9 are the parallel data of nine bits, and i0-i3 are four-bit counter values binarized from the I which corresponds to an index for 16-bit pseudo-orthogonal code. COPYRIGHT: (C)2011,JPO&INPIT |
