发明名称 Processor and method of control of processor
摘要 A processor including: a first storage unit that stores data; an error detection unit that detects an occurrence of error in data read out from the first storage unit; a second storage unit that stores data read out from the first storage unit based on a load request; a rerun request generation unit that generates a rerun request of a load request to the first storage unit in the same cycle as the cycle in which error of data is detected when the error detection unit detects the occurrence of error in data read out from the first storage unit by the load request; and an instruction execution unit that retransmits the load request to the first storage unit when data in which error is detected and a rerun request are given.
申请公布号 EP2323040(A1) 申请公布日期 2011.05.18
申请号 EP20100191077 申请日期 2010.11.12
申请人 FUJITSU LIMITED 发明人 SHIRAHIGE, YUJI;SUNAYAMA, RYUICHI
分类号 G06F12/08;G06F11/10 主分类号 G06F12/08
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