| 摘要 |
A clock control circuit includes a clock delay device, an edge detection device, a phase determination device and a delay control device. The clock delay device generates a delayed rising clock and a delayed falling clock by delaying a rising clock and a falling clock, which are transferred from a clock generation circuit, in response to a control signal, and to transfer the delayed rising clock and the delayed falling clock to a data output buffer. The edge detection device detects a difference between an edge timing of the delayed rising clock and an edge timing of the delayed falling clock to generate edge detection signals. The phase determination device detects a duty ratio of each of the edge detection signals to generate phase determination signals. The delay control device generates the control signal in response to the phase determination signals.
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