| 摘要 |
A real-time implementation of a subspace tracker is disclosed. Efficient architecture addresses the unique computational elements of the Fast Approximate Subspace Tracking (FAST) algorithm. Each of these computational elements can scale with the rank and size of the subspace. One embodiment of architecture described is implemented in digital hardware that performs variable rank subspace tracking using the FAST algorithm. In particular, the FAST algorithm is effectively implemented by a few processing elements, coupled with an efficient Singular Vector Decomposition (SVD), and the realization/availability of high density programmable logic devices. The architecture enables the ability to track the possibly changing dimension of the signal subspace.
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