发明名称 |
Single shared instruction predecoder for supporting multiple processors |
摘要 |
Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions to be issued within a common issue group by scheduling them for execution in different pipelines to execute at different times. |
申请公布号 |
US7945763(B2) |
申请公布日期 |
2011.05.17 |
申请号 |
US20060610110 |
申请日期 |
2006.12.13 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
LUICK DAVID A. |
分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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