| 摘要 |
A method for enabling management of fatal defects of semiconductor integrated patterns easily, the method enables storing of design data of each pattern designed by a semiconductor integrated circuit designer, as well as storing of design intent data having pattern importance levels ranked according to their design intents respectively. The method also enables anticipating of defects to be generated systematically due to the characteristics of the subject exposure system, etc. while each designed circuit pattern is exposed and delineated onto a wafer in a simulation carried out beforehand and storing those defects as hot spot information. Furthermore, the method also enables combining of the design intent data with hot spot information to limit inspection spots that might include systematic defects at high possibility with respect to the characteristics of the object semiconductor integrated circuit and shorten the defect inspection time significantly.
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