发明名称 |
VERFAHREN UND VORRICHTUNG ZUR ERKENNUNG VON TAKTGATTERGELEGENHEITEN BEI EINER ELEKTRONISCHEN SCHALTUNG IM PIPELINE-DESIGN |
摘要 |
<p>A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.</p> |
申请公布号 |
AT507520(T) |
申请公布日期 |
2011.05.15 |
申请号 |
AT20080787252T |
申请日期 |
2008.08.14 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
FERNSLER, MATTHEW;JACOBSON, HANS;SROUJI, JOHNY;SWANSON, TODD |
分类号 |
G06F1/32 |
主分类号 |
G06F1/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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