发明名称 TECHNIQUE FOR EVALUATING FABRICATION OF SEMICONDUCTOR COMPONENT AND WAFER
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a mechanism for analyzing a fabrication of a wafer. <P>SOLUTION: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes including the particular fabrication process indicated by the performance parameter value has been performed. <P>COPYRIGHT: (C)2011,JPO&INPIT</p>
申请公布号 JP2011097098(A) 申请公布日期 2011.05.12
申请号 JP20110009582 申请日期 2011.01.20
申请人 TAU-METRIX INC 发明人 AGHABABAZADEH MAJID;ESTABIL JOSE J;PAKDAMAN NADAR;STEINBRUECK GARY L;VICKERS JAMES S
分类号 H01L21/66;G01R31/28;G01R31/317;G01R31/3185;H01L23/544 主分类号 H01L21/66
代理机构 代理人
主权项
地址