STRUCTURES AND METHODS OF TRIMMING THRESHOLD VOLTAGE OF A FLASH EEPROM MEMORY

摘要

PURPOSE: A structure for controlling the threshold voltage of a flash EEPROM and a method thereof are provided to control the threshold voltage of an FET NVM cell in an MLC operation by applying a specific signal to the drain of the FET NVM cell. CONSTITUTION: In a structure for controlling the threshold voltage of a flash EEPROM and a method thereof, a first voltage is applied to a control gate. A second voltage is applied to the bulk of the FET NVM cell. A specific is applied to the drain of the repeatedly programmed FET NVM cell. The polarity of the first and second voltage is opposite to the polarity of the signal.