发明名称 HIGH-PRESSURE PROCESSING CHAMBER FOR SEMICONDUCTOR WAFER
摘要 PROBLEM TO BE SOLVED: To provide a processing chamber including an improved sealing means. SOLUTION: The processing chamber 101 includes a lower element 150, an upper element 110, and a seal-biasing device. The seal-biasing device is configured to maintain the upper element 110 against the lower element 150 to maintain a processing space 140. The seal-biasing device is further configured to generate sealing pressure in a seal-biasing cavity 115 that varies non-linearly with respect to processing pressure generated within the processing space 140. In one embodiment, the seal-biasing device is configured to minimize a non-negative net force against one of the upper element 110 and the lower element 150 above a threshold value. When it is assumed that P1 is the sealing pressure, P2 is the processing pressure, A1 is a cross-sectional area of the seal-biasing cavity, and A2 is a cross-sectional area of the processing space, the net force follows the expression P1*A1-P2*A2. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011097101(A) 申请公布日期 2011.05.12
申请号 JP20110014290 申请日期 2011.01.26
申请人 TOKYO ELECTRON LTD 发明人 JONES WILLIAM D
分类号 H01L21/304;H01L;H01L21/00 主分类号 H01L21/304
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