发明名称 |
DELAY LOCKED LOOP |
摘要 |
<p>PURPOSE: A delay locked loop is provided to obtain a reduce effect of a consumed current and rapid ability of operation by shortening a delay locking time through an open loop structure. CONSTITUTION: A delay amount pulse generating unit(210) generates a delay amount pulse having a pulse width corresponding to the delay among necessary for delay locking of a clock signal. A delay amount code unit(220) codes a delay amount necessary for delay locking by measuring the size of the delay among pulse. A delay line(230) delays the clock signal by responding to the code value. The delay amount pulse generating unit includes replica delay oscillator unit which generates a replica generating signal having a period corresponding to the replica delay. The delay amount pulse generating unit includes a pulse generating unit generating a delay amount pulse having a pulse width corresponding to the delay amount necessary for delay locking and a clock control unit outputting a clock signal by responding to the initialize signal.</p> |
申请公布号 |
KR101034617(B1) |
申请公布日期 |
2011.05.12 |
申请号 |
KR20090133433 |
申请日期 |
2009.12.29 |
申请人 |
HYNIX SEMICONDUCTOR INC. |
发明人 |
AHN, SEUNG JOON;LEE, JONG CHERN |
分类号 |
H03L7/081;G11C11/407;H03K5/13;H03K5/14 |
主分类号 |
H03L7/081 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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