发明名称 FAIL-SAFE SYSTEM
摘要 PROBLEM TO BE SOLVED: To execute recovery processing for preventing continuity of control from being interrupted by restarting a reset CPU from an initial state, and reading the final data value and address value stored in a data/address recording unit. SOLUTION: Each system includes a bus for data communication and a CPU device and a memory device connected to the bus. A continuity test processing unit for comparing and testing inter-bus information of each system is connected to each system. When the inter-bus information in the continuity test processing unit is not matched, it is determined that an error is caused. A reset processing unit generates a reset signal to any CPU or both system CPU on the basis of trigger information when it is determined that the error is caused by the continuity test processing unit. A data/address recording unit records information necessary for resuming processing from a prescribed address after the reset processing. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011095837(A) 申请公布日期 2011.05.12
申请号 JP20090246675 申请日期 2009.10.27
申请人 TOSHIBA CORP 发明人 MURAI JUN
分类号 G06F11/18 主分类号 G06F11/18
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