发明名称 MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM
摘要 <p>A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.</p>
申请公布号 EP2319044(A2) 申请公布日期 2011.05.11
申请号 EP20090800787 申请日期 2009.07.09
申请人 MICRON TECHNOLOGY, INC. 发明人 LABERGE, PAUL, A.;JEDDELOH, JOSEPH, M.;JOHNSON, JAMES, B.
分类号 G11C7/10;G11C5/02;G11C11/401;G11C11/4096;G11C29/02 主分类号 G11C7/10
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