| 摘要 |
The device has a non volatile electrically programmable and erasable memory point (PTM) comprising memory cells (CEL1, CEL2) respectively connected to bit lines using two bit line selection transistors. A common terminal (S1) between the bit line selection transistor (TSBL1) and a floating gate transistor (TGF1) of one memory cell is connected to a control gate (CG2) of another floating gate transistor (TGF2) of another memory cell. |
