| 摘要 |
1,083,881. Transistors. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. Aug. 27, 1964 [Aug. 30, 1963], No. 35121/64. Heading H1K. A field effect transistor with a variable-mu characteristic is provided by constructing the gate electrode region so that a small portion of its transverse dimension provides a mutual conductance effect different from that provided by the rest of the gate electrode. The invention is applicable to transistors operating in the depletion mode where the matching region provides a retarded controlled interruption effect which becomes effective after the main portion of the current path has been closed off and to operation in the enhancement mode wherein an advanced enhancement effect operates before the main path has opened. The special effect of the matching region may be produced by varying the effective width of the gate electrode in one portion or the thickness or the resistivity of the associated semi-conductor portion, or electrode positioning, or providing a small gap in the gate electrode which becomes effective for cut-off only at high gate voltages, or by varying the thickness of the insulation of the gate electrode, or by using material with different contact potential for part of the gate electrode. Fig. 1 shows an N-type silicon layer covered by source and drain electrodes 3 and 4 separated by a 20 Á gap which is covered by an insulating layer and metallic layer 6 to form the gate electrode. The metallic layer is cut away to provide a thin portion 7 which constitutes the matching region. Instead of thin portion 7, a gap of a few microns may be provided in the gate electrode which is bridged by a conductor and has a similar effect. In another embodiment, the source, drain and gate electrodes are annular in form, and a sector of the gate electrode is provided with a thicker insulator layer than the remainder of the gate electrode. Two or more gate electrodes may be provided some of which may act as a screen. Cadmium sulphide or germanium may be used as semi-conductor and may be in the form of layers on intrinsic silicon or insulating substrates and may form part of solid circuit arrangements. The invention is applicable to insulated gate or PN junction field effect transistors.
|
