发明名称 Generating a module interface for partial reconfiguration design flows
摘要 A method of processing a logical netlist for implementing a circuit design within a programmable logic device includes identifying a dynamically reconfigurable module (DRM) including at least one port from the logical netlist and determining whether the port connects with function logic for a function of the DRM. If the port connects with function logic, logic is inferred that connects the function logic with logic that is external to the DRM. If the port does not connect with function logic, logic is inferred that connects the port of the DRM with logic that is external to the DRM according to an attribute associated with the port. The logical netlist is updated to specify the inferred logic.
申请公布号 US7941777(B1) 申请公布日期 2011.05.10
申请号 US20070891141 申请日期 2007.08.08
申请人 XILINX, INC. 发明人 YOUNG JAY T.;LEAVESLEY, III W. STORY
分类号 G06F17/50 主分类号 G06F17/50
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