发明名称 Reading circuitry in memory
摘要 A reading circuit in a memory, having a first memory cell coupled to a first bit line and a second bit line, a second memory cell coupled to the second bit line and a third bit line and a third memory cell coupled to the third bit line and a fourth bit line, is provided. The reading circuitry includes a sensing circuit, a drain side bias circuit, a first selection circuit and a second selection circuit. The drain side bias circuit provides a drain side bias. The first selection circuit connects the second bit line to the drain side bias circuit to receive the drain side bias in a read operation mode. The second selection circuit connects the first bit line and the fourth bit line to the sensing circuit in the read operation mode, so that the sensing circuit senses a current of the first memory cell.
申请公布号 US7940565(B2) 申请公布日期 2011.05.10
申请号 US20100748030 申请日期 2010.03.26
申请人 MACRONIX INTERNATIONAL CO., LTD. 发明人 CHEN CHUNG-KUANG
分类号 G11C11/34 主分类号 G11C11/34
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