发明名称 Fractional delay-locked loops
摘要 A phase-locked loop includes a phase-to-digital converter that receives a first periodic input signal at a first input and a first feedback signal at a second input. The phase-to-digital converter generates digital signals. A digitally controlled oscillator includes a delay-locked loop that is responsive to the digital signals. The delay-locked loop generates a periodic output signal having an average frequency that is a product of a frequency of the first periodic input signal multiplied by a non-integer fractional number while a phase of the first periodic input signal is unchanging.
申请公布号 US7940098(B1) 申请公布日期 2011.05.10
申请号 US20100701346 申请日期 2010.02.05
申请人 ALTERA CORPORATION 发明人 KWASNIEWSKI TAD;ZARKESHVARI FARHAD
分类号 H03K7/06 主分类号 H03K7/06
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