发明名称 SEMICONDUCTOR MEMORY
摘要 PROBLEM TO BE SOLVED: To improve refresh characteristics by performing data rearrangement at a high speed. SOLUTION: In two memory blocks of memory blocks MB0-MBm, word lines are each driven to a selected state, and memory cell data is latched by a corresponding sense amplifier band. Then, data on a memory cell on one word line (sense amplifier) is read out to a global data line pair GIOP, and the read-out data is transferred to a rearrangement data line pair GRAP through a transfer circuit XFR. Subsequently, the data is transmitted to a memory cell on a selected word line in the other memory block through the rearrangement data line pair GRAP. In the data rearrangement, data is transferred internally to perform data rearrangement under the control of local control circuits LCTL0-LCTLm and a main control circuit MCTL. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011090778(A) 申请公布日期 2011.05.06
申请号 JP20100277078 申请日期 2010.12.13
申请人 RENESAS ELECTRONICS CORP 发明人 SHIMANO HIROKI;HASHIZUME TAKESHI;ARIMOTO KAZUTAMI;FUJINO TAKESHI
分类号 G11C29/04;G11C11/401;G11C29/12 主分类号 G11C29/04
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