| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a data processor which can reduce the power consumption of a memory and shorten the latency of memory operation when memory returns from a low power consumption state and starts the operation. <P>SOLUTION: The data processor includes a bus controller (104) which arbitrates and receives an input bus access request, and a memory controller (105) which receives the bus access request to a memory (106) received by the bus controller and controls the memory. The bus controller notifies the memory controller that it has received a new bus access request to the memory. The notified memory controller cancels the low power consumption state of the memory earlier than answering the bus access request when the memory is in the low power consumption state. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
