发明名称 DECODER
摘要 <p><P>PROBLEM TO BE SOLVED: To output decoded data in a plurality of phases when decoding the encoded data for each block consisting of a specified number of data. <P>SOLUTION: An input buffer 201 divides inputted encoded data into those of odd numbers and those of even numbers, for outputting them in parallel. Decoding sections 202a and 202b perform inverse quantization on the inputted encoded data so that a difference value is decoded. A selector 204 selects a decoded data from an adder 203 except for first data, and outputs them as the decoded data of even number, meanwhile supplies it to an adder 205 as a previous value. The adder 205 adds a decoded difference value of the encoded data of odd number, that is inputted from the decoding section 202b, to the decoded data of even number which is inputted from the selector 204 as a preceding value, to generate a decoded data of odd number, which is supplied to the adder 203 as a preceding value through a buffer 206. <P>COPYRIGHT: (C)2011,JPO&INPIT</p>
申请公布号 JP2011091590(A) 申请公布日期 2011.05.06
申请号 JP20090242952 申请日期 2009.10.22
申请人 VICTOR CO OF JAPAN LTD 发明人 MATSUMOTO EIJI;AIBA HIDEKI
分类号 H04N19/426;H04N19/436;H04N19/44;H04N19/50 主分类号 H04N19/426
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