发明名称 |
METHOD AND APPARATUS USED FOR THE PHYSICAL VALIDATION OF INTEGRATED CIRCUITS |
摘要 |
The present invention involves a method and an apparatus used for the physical design validation of integrated circuits. Said method includes the following steps: the original circuit netlist of an integrated circuit and the layout data of said integrated circuit are compared; labels are assigned to the input and output terminals of the components in said integrated circuit based on the results of the comparison. |
申请公布号 |
WO2011051797(A2) |
申请公布日期 |
2011.05.05 |
申请号 |
WO2010IB02782 |
申请日期 |
2010.10.28 |
申请人 |
SYNOPSYS, INC.;KU, CHIU-YU |
发明人 |
KU, CHIU-YU |
分类号 |
G06F11/00;G06F17/50 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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