发明名称 APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES
摘要 A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
申请公布号 US2011102042(A1) 申请公布日期 2011.05.05
申请号 US20110987106 申请日期 2011.01.08
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 CANNON ETHAN H.;KLEINOSOWSKI AJ;MULLER K. PAUL;NING TAK H.;OLDIGES PHILIP J.;SIGAL LEON J.;WARNOCK JAMES D.;WENDEL DIETER
分类号 H03K3/00 主分类号 H03K3/00
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