PROGRAMMABLE DIGITAL CLOCK CONTROL SCHEME TO MINIMIZE SPUR EFFECT ON A RECEIVER

摘要

A device includes an analog front end for receiving a radio frequency (RF) signal. The analog front end contains a local oscillator that is tuned to a local oscillation frequency for down-converting the received RF signal to a first intermediate frequency (IF) signal. An analog-to-digital converter module converts the first IF signal to a digital baseband signal. The device also includes a digital processing unit for processing the baseband signal. The digital processing unit generates multiple clock signals from a reference oscillator having digitally adjustable reference frequency. The reference frequency and the multiple clock signals may interfere with the local oscillator and generate several frequency spurs that may fall within the bandwidth of the received RF signal. In a preferred embodiment, the digital processing unit adjusts the reference frequency by a certain amount so that the spurs do not fall within the RF signal bandwidth.