| 摘要 |
An automatic voltage compensation circuit in a voltage regulator compensates the output voltage for a voltage drop along lines leading to a remote load. A load capacitor is connected across the load for providing a low impedance across the load during a test phase of the regulator. In one embodiment, during the test phase, the load current is changed up or down a small percentage (e.g., 10%). As a result, the regulator voltage changes due only to the line resistance since the load is bypassed by the load capacitor. The voltage drop at full load current is then derived by detecting the change in regulator output voltage (a fractional voltage drop) and multiplying it. The normal mode is resumed, and the derived voltage drop is added to the regulator output by either compensating the feedback loop or by adding the voltage drop to the output of the regulator.
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