| 摘要 |
A bus system in accordance with an exemplary aspect of the present invention includes a bus master that performs a preparation for a next access after receiving a write response signal indicating a write result of data in a write access; a bus slave that writes data indicated by a write data signal according to an output of the write data signal from the bus master in the write access, and outputs an authentic write response signal in the writing to the bus master; a bus that connects the bus master and the bus slave, and includes a register slice; and a signal generating unit that outputs a dummy write response signal to the bus master when an end of the write data signal output from the bus master is detected.
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